Memory array

ABSTRACT

A memory array including a plurality of word lines, a plurality of first source/drain lines, a plurality of second source/drain lines, and a plurality of memory units. Each memory unit includes a gate electrode coupled to one of the word lines, a first source/drain region coupled to one of the first source/drain lines or first bit lines, a second source/drain region coupled to one of the second source/drain lines or second bit lines, a first spacer between the first source/drain region and the gate electrode to store electrons or electric charges, and a second spacer between the second source/drain region and the gate electrode to store electrons or electric charges.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, and morespecifically to a memory array with increased data throughput.

2. Description of the Related Art

Non-volatile read only memory (ROM) retains information even if power iscut off. Erasable ROM types comprise Mask ROM, EPROM, EEPROM, and FlashMemory, of which Mask ROM cannot modify stored data, and is suited tolarge fabrications. Additionally, Flash Memory, using electrons enteringand exiting floating gate to store information, is non-volatile andaccessible, and can also restore and access information even when poweris not provided.

FIG. 1 a is a cross section of a conventional flash memory unit duringprogramming. When programming is performed, a high voltage is applied toa control gate electrode 105 and a drain region 101 a, and thenelectrons penetrate through a gate oxide layer 102 to a floating gateelectrode 103 from the drain region 101 a in a silicon substrate 101.

FIG. 1 b is a cross section of a conventional flash memory unit duringerasure. When erasure is performed, a negative or zero voltage isapplied to the control gate electrode 105, and a high voltage is appliedto the drain region 101 a in the silicon substrate 101. Electrons thenpenetrate through the gate oxide layer 102 back to the drain region 101a from the floating gate electrode 103.

As a result, one set of data can be programmed or erased each time bythe conventional flash memory unit, that is, the maximum set count ofdata programmed or erased each time equals the number of memory units.

FIG. 1 c is a cross section of a conventional programmed Mask ROM. Theprogramming process is disclosed as follows. First, a silicon substrate120 having a memory unit, such as a MOS transistor, thereon is provided.An oxide layer 122 is then formed over the silicon substrate 120. Thememory unit comprises a gate electrode 123, such as a polysilicon layer,and source/drain regions 121 a and 121 b, such as n⁺ or p⁺ diffusionregion, here, the source/drain regions 121 a and 121 b are n⁺ diffusionregions.

Next, a lithography process is performed using a code mask to form apatterned photoresist layer over a part of the gate electrode 123 andthe source/drain regions 121 a and 121 b. Channel implantation with thesilicon substrate 120 having memory units is then performed to completethe memory unit coding.

When the gate electrode 123 is uncovered by the patterned photoresist,the memory unit is defined as logic “1” due to implantation of thechannel region 124, to the contrary, when the gate electrode 123 iscovered by the patterned photoresist, the memory unit is defined aslogic “0”, because the channel region 124 cannot be implanted.

Implantation Programming is completed by implanting ions into channelregion to adjust the threshold voltage. This process is performed afterforming the MOS transistor, and before forming contacts or inter layerdielectrics (ILD).

As integration density is increased, reduced time and memory unit size,and increased quantity and speed of data treatment are required forfabricating Mask ROMs.

SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to provide variousmulti-bit memory arrays to increase memory unit density, and thereby,throughput.

To achieve this and other objects, the present invention provides amemory array, comprising a plurality of word lines, a plurality of firstsource/drain lines, a plurality of second source/drain lines, and aplurality of memory units. Each memory unit comprises a gate electrodecoupled to one of the word lines, a first source/drain region coupled toone of the first source/drain lines or first bit lines, a secondsource/drain region coupled to one of the second source/drain lines orsecond bit lines, a first spacer between the first source/drain regionand the gate electrode to store electrons or electric charges, a secondspacer between the second source/drain region and the gate electrode tostore electrons or electric charges.

The present invention also provides another memory array, comprising aplurality of word lines, a plurality of first source/drain lines, aplurality of second source/drain lines, and a plurality of memory units.Each memory unit comprises a gate electrode coupled to one of the wordlines, a first source/drain region coupled to one of the firstsource/drain lines or first bit lines, a second source/drain regioncoupled to one of the second source/drain lines or second bit lines, aprogrammed source/drain extended area between the gate electrode and thefirst or second source/drain region to store or keep electricinformation.

The present invention further provides another memory array, comprisinga plurality of word lines, a plurality of first source/drain lines, aplurality of second source/drain lines, and a plurality of memory units.Each memory unit comprises a gate electrode coupled to one of the wordlines, a first source/drain region coupled to one of the firstsource/drain lines or first bit lines, a second source/drain regioncoupled to one of the second source/drain lines or second bit lines, ananti-fuse between the gate electrode and the first or secondsource/drain region.

Further scope of the applicability of the present invention will becomeapparent from the detailed description given hereinafter. However, itshould be understood that the detailed description and specificexamples, while indicating preferred embodiments of the invention, aregiven by way of illustration only, since various changes andmodifications within the spirit and scope of the invention will becomeapparent to those skilled in the art from this detailed description.

A detailed description is given in the following embodiments withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from thedetailed description given hereinafter and the accompanying drawings,which are given by way of illustration only, and thus are not limitativeof the present invention, and in which:

FIG. 1 a is a cross section of a conventional flash memory unit duringprogramming.

FIG. 1 b is a cross section of a conventional flash memory unit duringerasure.

FIG. 1 c is a cross section of a conventional programmed Mask ROM.

FIG. 2 a is a cross section of a multi-bit EPROM unit of the presentinvention.

FIG. 2 b is a cross section of a Mask ROM unit of the present invention.

FIG. 2 c is a cross section of a One Time Programmable anti-fuse ROMunit of the present invention.

FIG. 3 a shows a single multi-bit memory unit in the first embodiment ofthe present invention.

FIG. 3 b shows a multi-bit memory array in the first embodiment of thepresent invention.

FIG. 3 c shows an equivalent circuit of the multi-bit memory array inFIG. 3 b.

FIG. 4 a shows a single multi-bit memory unit in the second embodimentof the present invention.

FIG. 4 b shows a multi-bit memory array in the second embodiment of thepresent invention.

FIG. 4 c shows an equivalent circuit of the multi-bit memory array inFIG. 4 b.

FIGS. 5 a and 5 b show two single multi-bit memory units in the thirdembodiment of the present invention.

FIG. 5 c shows a multi-bit memory array in the third embodiment of thepresent invention.

FIG. 5 d shows an equivalent circuit of the multi-bit memory array inFIG. 5 c.

FIGS. 6 a and 6 b show two single multi-bit memory units in the fourthembodiment of the present invention.

FIG. 6 c shows a multi-bit memory array in the fourth embodiment of thepresent invention.

FIG. 6 d shows an equivalent circuit of the multi-bit memory array inFIG. 6 c.

FIGS. 7 a and 7 b show two single multi-bit memory units in the fifthembodiment of the present invention.

FIG. 7 c shows a multi-bit memory array in the fifth embodiment of thepresent invention.

FIG. 7 d shows an equivalent circuit of the multi-bit memory array inFIG. 7 c.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2 a is a cross section of the multi-bit EPROM unit of the presentinvention. The multi-bit memory unit comprises a semiconductor substrate201 having a source/drain region therein, a gate electrode 202, such asa polysilicon layer, on the semiconductor substrate 201, a gatedielectric layer 203 a, such as a gate oxide layer, between the gateelectrode 202 and the semiconductor substrate 201, a spacer 204, such asa nitride layer, on a sidewall of the gate electrode 202 to storeelectrons or electric charges, an oxide layer 203 b between the spacer204 and the gate electrode 202, and a salicide layer 205, such as TiSi₂,CoSi₂ or NiSi, over the gate electrode 202 and the source/drain region.The memory unit further comprises a dielectric layer, such as an oxidelayer, over the semiconductor substrate 201 and the above elements, anda contact plug filled with a conductive layer in the dielectric layer toconnect the source/drain region installed between gate electrodes and asubsequently formed bit line.

FIG. 2 b is a cross section of the multi-bit Mask ROM of the presentinvention. The multi-bit memory unit comprises a semiconductor substrate220 having a gate dielectric layer 222 a and a gate electrode 223thereon and a source/drain extension area 221 therein under one side ofthe gate electrode 223, a spacer 224 on a sidewall of the gate electrode223, an oxide layer 222 b between the spacer 224 and the gate electrode223, a source/drain region in the semiconductor substrate 220, and asalicide layer 225 over the gate electrode 223 and the source/drainregion, wherein the source/drain extension area 221 is formed using aphotoresist layer and the gate electrode 223 as masks formed by a codemask, and the source/drain region is formed by implanting thesemiconductor substrate 220 with As or P ions using the gate electrode223 and the spacer 224 as masks.

If the source/drain extension area 221 is not formed between thesource/drain region and the gate electrode 223, the threshold voltage ofthe memory unit may increase. When accessing data, if a normal voltageis applied to the gate electrode 223, the source/drain region can not beconducted, producing merely lowered leakage current, thus the logic “0”is accessed. If the source/drain extension area 221 is formed betweenthe source/drain region and the gate electrode 223, the thresholdvoltage of the memory unit may decrease. When accessing data, if anormal voltage is applied to the gate electrode 223, the source/drainregion can be conducted, and logic “1” is accessed. Thus, the memoryunit is accessed as logic “1”, when the source/drain extension 221 isformed coupled to the gate electrode 223, and the memory unit isaccessed as logic “0”, when the source/drain extension 221 is notcoupled to the gate electrode 223.

FIG. 2 c is a cross section of the One Time Programmable anti-fuse ROMof the present invention. The memory unit comprises a semiconductorsubstrate 230 having a gate dielectric layer 232 a and a gate electrode233 thereon and a source/drain extension area 231 therein under one sideof the gate electrode 233, a spacer 224 on a sidewall of the gateelectrode 233, an insulation layer 232 b between the spacer 234 and thegate electrode 233, a source/drain region in the semiconductor substrate230, and a salicide layer 235 over the gate electrode 233 and thesource/drain region, wherein the source/drain extension area 231 isformed using the gate electrode 233 as a mask, and the source/drainregion is formed by implanting the semiconductor substrate 230 using thegate electrode 233 and the spacer 234 as masks. After thermal process,the source/drain extension area 231 diffuses toward under the gateelectrode 233, resulting in isolation between the gate electrode 233 andthe source/drain extension area 231 by the gate dielectric layer 232 c.The gate dielectric layer 232 c can be broken down to create leakage byselectively applying high voltage, used as anti-fuse memory.

If the anti-fuse between the source/drain region and the gate electrode233 is not breakdown, the electric leakage of the memory unit maydecrease. When accessing data, if a normal voltage is applied to thegate electrode 233, the source/drain region can not be conducted,producing merely lowered leakage current, thus the logic “0” isaccessed. If the anti-fuse between the source/drain region and the gateelectrode 233 is breakdown, the electric leakage of the memory unit mayincrease. When accessing data, if a normal voltage is applied to thegate electrode 233, high leakage current may occur, whereby the logic“1”, is accessed. Thus, the memory unit is accessed as logic “1” whenthe anti-fuse is-breakdown, and logic “0” when the anti-fuse is notbreakdown.

FIRST EMBODIMENT

FIG. 3 a shows a single multi-bit memory unit in the first embodiment ofthe present invention, FIG. 3 b shows a memory array in the firstembodiment of the present invention, and FIG. 3 c shows an equivalentcircuit of the memory array in FIG. 3 b.

Referring to FIG. 3 a, a semiconductor substrate (not shown) having themulti-bit memory unit shown in FIG. 2 a or 2 b is provided, with anactive area 30 defined therein.

The multi-bit memory unit comprises a word line WL¹, a first bit lineBL³, a second bit line BL⁴, a first connection point C¹, and a secondconnection point C², wherein the word line is the gate electrode, andthe connection points are contact plugs.

The word line WL¹ is perpendicular to the first bit line BL³ and thesecond bit line BL⁴. The first bit line BL³ is parallel to the secondbit line BL⁴, and the first bit line BL³ and the second bit line BL⁴ areseparated into two portions by the word line WL¹. The first connectionpoint C¹ electrically connects to the first bit line BL³, and the secondconnection point C² electrically connects to the second bit line BL⁴,wherein the first connection point C¹ and the second connection point C²are located on different sides separated by the word line WL¹. Theactive area 30 comprises the above elements. The active area 30 isrectangular, and the first connection point C¹ and the second connectionpoint C² are respectively located on the diagonal position thereof.

Referring to FIG. 3 b, the memory array comprises word lines WL¹, WL²,and WL³, bit lines BL¹, BL², BL³, BL⁴, BL⁵, and BL⁶, connection pointsC¹ and C², memory unit 301, and active areas 30, wherein the memory unit301 is the single multi-bit memory unit shown in FIG. 3 a. Eachconnection point can be jointly used by adjacent memory units, forexample, the second connection point C² is jointly used by the memoryunit 301 and its adjacent memory unit to form the electrical connection,as shown in FIG. 3 c.

SECOND EMBODIMENT

FIG. 4 a shows a single multi-bit memory unit in the second embodimentof the present invention, FIG. 4 b shows a memory array in the secondembodiment of the present invention, and FIG. 4 c shows an equivalentcircuit of the memory array in FIG. 4 b.

Referring to FIG. 4 a, a semiconductor substrate (not shown) having themulti-bit memory unit shown in FIG. 2 a or 2 b is provided, with anactive area 40 defined therein.

The multi-bit memory unit comprises a word line WL¹, a first bit lineBL³, a second bit line BL⁴, a first connection point C¹, and a secondconnection point C², wherein the word line is the gate electrode, andthe connection points are contact plugs.

The word line WL¹ is perpendicular to the first bit line BL³ and thesecond bit line BL⁴. The first bit line BL³ is parallel to the secondbit line BL⁴, and the first bit line BL³ and the second bit line BL⁴ areseparated into two portions by the word line WL¹. The first connectionpoint C¹ electrically connects to the first bit line BL³, and the secondconnection point C² electrically connects to the second bit line BL⁴,wherein the first connection point C¹ and the second connection point C²are located on different sides separated by the word line WL¹. Theactive area 40 comprises the above elements. The active area 40 isrectangular, and the first connection point C¹ and the second connectionpoint C² are respectively located on two ends of the active area 40. Theincluded angle between the active area 40 and the word line WL¹ is lessthan 90°.

Referring to FIG. 4 b, the memory array comprises word lines WL¹, WL²,WL³, and WL⁴, bit lines BL¹, BL², BL³, and BL⁴, connection points C¹ andC², memory unit 401, and active areas 40, wherein the memory unit 401 isthe single multi-bit memory unit shown in FIG. 4 a. Each connectionpoint can be jointly used by adjacent memory units, for example, thesecond connection point C² is jointly used by the memory unit 401 andits adjacent memory unit to form the electrical connection, as shown inFIG. 4 c.

THIRD EMBODIMENT

FIGS. 5 a and 5 b show two single multi-bit memory units in the thirdembodiment of the present invention, FIG. 5 c shows a memory array inthe third embodiment of the present invention, and FIG. 5 d shows anequivalent circuit of the memory array in FIG. 5 c.

Referring to FIGS. 5 a and 5 b, a semiconductor substrate (not shown)having a multi-bit memory unit shown in FIG. 2 a or 2 b is provided,with an active area 50 defined therein.

Referring to FIG. 5 a, one of the two multi-bit memory units isdisclosed as follows. The multi-bit memory unit comprises a word lineWL¹, a first bit line BL³, a second bit line BL⁴, a first connectionpoint C¹, and a second connection point C², wherein the word line is thegate electrode, and the connection points are contact plugs.

The word line WL¹ is perpendicular to the first bit line BL³ and thesecond bit line BL⁴. The first bit line BL³ is parallel to the secondbit line BL⁴, and the first bit line BL³ and the second bit line BL⁴ areseparated into two portions by the word line WL¹. The first connectionpoint C¹ electrically connects to the first bit line BL³, and the secondconnection point C² electrically connects to the second bit line BL⁴,wherein the first connection point C¹ and the second connection point C²are located on different sides separated by the word line WL¹. Theactive area 50 comprises the above elements. The active area 50 isrectangular, and the first connection point C¹ and the second connectionpoint C² are respectively located on two ends of the active area 50. Theincluded angle between the active area 50 and the word line WL¹ is lessthan 90°.

Referring to FIG. 5 b, another multi-bit memory unit is disclosed asfollows. The multi-bit memory unit comprises a word line WL², a firstbit line BL³, a second bit line BL⁴, a second connection point C², and athird connection point C³, wherein the word line is the gate electrode,and the connection points are contact plugs.

The word line WL² is perpendicular to the first bit line BL³ and thesecond bit line BL⁴. The first bit line BL³ is parallel to the secondbit line BL⁴, and the first bit line BL³ and the second bit line BL⁴ aresegregated to two portions by the word line WL². The second connectionpoint C² electrically connects to the first bit line BL³, and the thirdconnection point C³ electrically connects to the second bit line BL⁴,wherein the second connection point C² and the third connection point C³are located on different sides separated by the word line WL². Theactive area 50 comprises the above elements. The active area 50 isrectangular, and the second connection point C² and the third connectionpoint C³ are respectively located on two ends of the active area 50. Theincluded angle between the active area 50 and the word line WL² is lessthan 90°.

Referring to FIG. 4 c, the memory array comprises word lines WL¹, WL²,and WL³, bit lines BL¹, BL², BL³, BL⁴, BL⁵, and BL⁶, connection pointsC¹, C², and C³, memory unit 501, and active areas 50, wherein the memoryunit 501 is the single multi-bit memory unit shown in FIG. 5 a or 5 b.Each connection point can be jointly used by four adjacent memory units,for example, the second connection point C² is jointly used by thememory unit 501 and its adjacent three memory units to form theelectrical connection, as shown in FIG. 5 c.

FOURTH EMBODIMENT

FIGS. 6 a and 6 b show two single multi-bit memory units in the fourthembodiment of the present invention, FIG. 6 c shows a memory array inthe fourth embodiment of the present invention, and FIG. 6 d shows anequivalent circuit of the memory array in FIG. 6 c.

Referring to FIGS. 6 a and 6 b, a semiconductor substrate (not shown)having a multi-bit memory unit shown in FIG. 2 a or 2 b is provided,with an active area 60 defined therein.

Referring to FIG. 6 a, one of the two multi-bit memory units isdisclosed as follows. The multi-bit memory unit comprises a word lineWL¹, a first bit line BL³, a second bit line BL⁴, a first connectionpoint C¹, and a second connection point C², wherein the word line is thegate electrode, and the connection points are contact plugs.

The word line WL¹ is perpendicular to the first bit line BL³ and thesecond bit line BL⁴. The first bit line BL³ is parallel to the secondbit line BL⁴, and the first bit line BL³ and the second bit line BL⁴ areseparated into two portions by the word line WL¹. The first connectionpoint C¹ electrically connects to the first bit line BL³, and the secondconnection point C² electrically connects to the second bit line BL⁴,wherein the first connection point C¹ and the second connection point C²are located on different sides separated by the word line WL¹. Theactive area 60 comprises the above elements. The active area 60 isZ-shaped, comprising a main area and two extended areas, with the twoextended areas perpendicularly connecting to two ends of the main arearespectively. A first source/drain region is formed in one of theextended areas and a part of the main area, and a second source/drainregion is formed in another extended area and a part of the main area.Therefore, the first connection point C¹ corresponding to the firstsource/drain region and the second connection point C² corresponding tothe second source/drain region are respectively located on the terminalof the extended areas.

Referring to FIG. 6 b, another multi-bit memory unit is disclosed asfollows. The multi-bit memory unit comprises a word line WL², a secondbit line BL⁴, a third bit line BL⁵, a second connection point C², and athird connection point C³, wherein the word line is the gate electrode,and the connection points are contact plugs.

The word line WL² is perpendicular to the second bit line BL⁴ and thethird bit line BL⁵. The second bit line BL⁴ is parallel to the third bitline BL⁵, and the second bit line BL⁴ and the third bit line BL⁵ areseparated to two portions by the word line WL². The second connectionpoint C² electrically connects to the second bit line BL⁴, and the thirdconnection point C³ electrically connects to the third bit line BL⁵,wherein the second connection point C² and the third connection point C³are located on different sides separated by the word line WL². Theactive area 60 comprises the above elements. The active area 60 isZ-shaped, comprising a main area and two extended areas, with the twoextended areas perpendicularly connecting to two ends of the main arearespectively. The second connection point C² and the third connectionpoint C³ are respectively located at the terminus of the extended areas.

Referring to FIG. 6 c, the memory array comprises word lines WL¹, WL²,and WL³, bit lines BL¹, BL², BL³, BL⁴, BL⁵, BL⁶, and BL⁷, connectionpoints C¹, C², and C³, memory unit 601, and active areas 60, wherein thememory unit 601 is the single multi-bit memory unit shown in FIG. 6 a or6 b. Each connection point can be jointly used by four adjacent memoryunits, for example, the second connection point C² is jointly used bythe memory unit 601 and its adjacent three memory units to form theelectrical connection, as shown in FIG. 6 c.

FIFTH EMBODIMENT

FIGS. 7 a and 7 b show two single multi-bit memory units in the fifthembodiment of the present invention, FIG. 7 c shows a memory array inthe fifth embodiment of the present invention, and FIG. 7 d shows anequivalent circuit of the memory array in FIG. 7 c.

Referring to FIGS. 7 a and 7 b, a semiconductor substrate (not shown)having a multi-bit memory unit shown in FIG. 2 a or 2 b is provided,with an active area 70 defined therein.

Referring to FIG. 7 a, the two multi-bit memory units are disclosed asfollows. The multi-bit memory unit comprises a word line WL¹ or WL², afirst bit line BL³, a first connection point C¹, wherein the word lineis the gate electrode, and the connection point is contact plug.

The word line WL¹ or WL² is perpendicular to the first bit line BL³,thus the first bit line BL³ is separated to two portions thereby. Thefirst connection point C¹ is located on one of the separated sides bythe word line WL¹ or WL², and electrically connects to the first bitline BL³. The active area 70 comprises the above elements. The activearea 70 is T-shaped, comprising a main area and an extended area, withone end of the main area connecting to the middle of the extended area.The main area is parallel to the first bit line BL³ (the first sourceline) corresponding thereto. The extended area is parallel to the wordline corresponding thereto.

Referring to FIG. 7 c, the memory array comprises word lines WL¹ andWL², bit lines BL¹, BL², BL³, BL⁴, BL⁵, and BL⁶, connection points C¹,C¹¹¹, and C¹¹², memory unit 701, and active areas 70, wherein the memoryunit 701 is the single multi-bit memory unit shown in FIG. 7 a or 7 b.Each connection point corresponding to the drain area can be jointlyused by two adjacent memory units in the same row, and the source areainstalled on the same column can be jointly used by each memory unit inthe same column. Additionally, memory units connect to the additionalmetal line M¹¹ or M¹² by the connection point C¹¹¹ or C¹¹². Referring toFIG. 7 d, the first connection point C¹ is jointly used by the memoryunit 701 and its adjacent memory unit in the same row to form theelectrical connection, and the source area, such as source-1, installedon the same column can be jointly used by each memory unit in the samecolumn. Additionally, memory units connect to the additional metal lineM¹¹ or M¹² by the connection point C¹¹¹ or C¹¹².

The present invention provides two blocks in a memory unit to storedata, that is, two sets of data can be programmed or erased,simultaneously. The maximum set count of data programmed or erased eachtime is twice the number of memory units.

While the invention has been described by way of example and in terms ofthe preferred embodiments, it is to be understood that the invention isnot limited to the disclosed embodiments. To the contrary, it isintended to cover various modifications and similar arrangements (aswould be apparent to those skilled in the art). Therefore, the scope ofthe appended claims should be accorded the broadest interpretation so asto encompass all such modifications and similar arrangements.

1. A memory array, comprising: a plurality of word lines; a plurality offirst source/drain lines; a plurality of second source/drain lines; anda plurality of memory units, comprising: a gate electrode, coupled toone of the word lines; a gate dielectric layer laid below the gateelectrode; a first source/drain region, coupled to one of the firstsource/drain lines or first bit lines, further comprising a firstmulti-layer dielectric spacer formed between the first source/drainregion and the gate electrode to store electrons or electric charges;and a second source/drain region, coupled to one of the secondsource/drain lines or second bit lines, further comprising a secondmulti-layer dielectric spacer formed between the second source/drainregion and the gate electrode to store electrons or electric charges; ametal-semiconductor compound layer formed over the gate electrode, firstsource/drain region and second source/drain region; a semiconductorchannel formed between said first source/drain region and secondsource/drain region.
 2. The memory array as claimed in claim 1, whereinthe memory units are readable, writeable, and erasable.
 3. The memoryarray as claimed in claim 1, wherein the word lines are gate electrodelines of the gate electrodes.
 4. The memory array as claimed in claim 1,wherein the first source/drain region of each memory unit couples to thecorresponding first source/drain line or the first bit line by a contactplug.
 5. The memory array as claimed in claim 1, wherein the secondsource/drain region of each memory unit couples to the correspondingsecond source/drain line or the second bit line by a contact plug. 6.The memory array as claimed in claim 1, wherein an active area of eachmemory unit comprises the first source/drain region, the secondsource/drain region, and a channel between the first and secondsource/drain regions, and the active area is perpendicular to the wordline.
 7. The memory array as claimed in claim 1, wherein an active areaof each memory unit comprises the first source/drain region, the secondsource/drain region, and a channel between the first and secondsource/drain regions, and an included angle between the active area andthe word line is less than 90°.
 8. The memory array as claimed in claim1, wherein an active area of each memory unit comprises the firstsource/drain region, the second source/drain region, and a channelbetween the first and second source/drain regions, and the active areais Z-shaped, comprising a main area and two extended areas, with the twoextended areas perpendicularly connecting to two ends of the main arearespectively, and the first source/drain region is in one of theextended areas and a part of the main area, and the second source/drainregion is in another extended area and a part of the main area.
 9. Thememory array as claimed in claim 1, wherein an active area of eachmemory unit comprises the first source/drain region, the secondsource/drain region, and a channel between the first and secondsource/drain regions, and the active area is T-shaped, comprising a mainarea and an extended area, wherein the end of the main area connects tothe middle of the extended area, and the active area is parallel to thefirst source/drain line or the first bit line corresponding thereto, andthe extended area is parallel to the word line corresponding thereto,and the first source/drain region is in a part of the main area, and thesecond source/drain region is in the extended area and a part of themain area.
 10. A memory array, comprising: a plurality of word lines; aplurality of first source/drain lines; a plurality of secondsource/drain lines; and a plurality of memory units, comprising: a gateelectrode, coupled to one of the word lines; a gate dielectric layerlaid below the gate electrode; a first source/drain region, coupled toone of the first source/drain lines or first bit lines; and a secondsource/drain region, coupled to one of the second source/drain lines orsecond bit lines, further comprising a programmable source/drainextended doped area formed between the gate electrode and the first orsecond source/drain region for storing or keeping electric information;a metal-semiconductor compound layer formed over the gate electrode,first source/drain region and second source/drain region; asemiconductor channel formed between said first source/drain region andsecond source/drain region.
 11. The memory array as claimed in claim 10,wherein the memory units are Mask ROM.
 12. The memory array as claimedin claim 10, wherein the word lines are gate electrode lines of the gateelectrodes.
 13. The memory array as claimed in claim 10, wherein thefirst source/drain region of each memory unit couples to thecorresponding first source/drain line or the first bit line by a contactplug.
 14. The memory array as claimed in claim 10, wherein the secondsource/drain region of each memory unit couples to the correspondingsecond source/drain line or the second bit line by a contact plug. 15.The memory array as claimed in claim 10, wherein an active area of eachmemory unit comprises the first source/drain region, the secondsource/drain region, and a channel between the first and secondsource/drain regions, and the active area is perpendicular to the wordline.
 16. The memory array as claimed in claim 10, wherein an activearea of each memory unit comprises the first source/drain region, thesecond source/drain region, and a channel between the first and secondsource/drain regions, and an included angle between the active area andthe word line is less than 90°.
 17. The memory array as claimed in claim10, wherein an active area of each memory unit comprises the firstsource/drain region, the second source/drain region, and a channelbetween the first and second source/drain regions, and the active areais Z-shaped, comprising a main area and two extended areas, with the twoextended areas perpendicularly connecting to two ends of the main arearespectively, with the first source/drain region in one of the extendedareas and a part of the main area, and the second source/drain region inanother extended area and a part of the main area.
 18. The memory arrayas claimed in claim 10, wherein an active area of each memory unitcomprises the first source/drain region, the second source/drain region,and a channel between the first and second source/drain regions, and theactive area is T-shaped, comprising a main area and an extended area,wherein the end of the main area connects to the middle of the extendedarea, and the active area is parallel to the first source/drain line orthe first bit line corresponding thereto, and the extended area isparallel to the word line corresponding thereto, with the firstsource/drain region in a part of the main area, and the secondsource/drain region in the extended area and a part of the main area.19. A memory array, comprising: a plurality of word lines; a pluralityof first source/drain lines; a plurality of second source/drain lines;and a plurality of memory units, comprising: a gate electrode, coupledto one of the word lines; a dielectric spacer formed on the sidewalls ofsaid gate electrode; a gate dielectric layer laid below the gateelectrode; a first source/drain region, coupled to one of the firstsource/drain lines or first bit lines; and a second source/drain region,coupled to one of the second source/drain lines or second bit lines,further comprising an anti-fuse dielectric formed between the gateelectrode and the first or second source/drain region; ametal-semiconductor compound layer formed over the gate electrode, firstsource/drain region and second source/drain region; a semiconductorchannel formed between said first source/drain region and secondsource/drain region.
 20. The memory array as claimed in claim 19,wherein the memory units are One Time Programmable ROM.
 21. The memoryarray as claimed in claim 19, wherein the word lines are gate electrodelines of the gate electrodes.
 22. The memory array as claimed in claim19, wherein the first source/drain region of each memory unit couples tothe corresponding first source/drain line or the first bit line by acontact plug.
 23. The memory array as claimed in claim 19, wherein thesecond source/drain region of each memory unit couples to thecorresponding second source/drain line or the second bit line by acontact plug.
 24. The memory array as claimed in claim 19, wherein anactive area of each memory unit comprises the first source/drain region,the second source/drain region, and a channel between the first andsecond source/drain regions, and the active area is perpendicular to theword line.
 25. The memory array as claimed in claim 19, wherein anactive area of each memory unit comprises the first source/drain region,the second source/drain region, and a channel between the first andsecond source/drain regions, and an included angle between the activearea and the word line is less than 90°.
 26. The memory array as claimedin claim 19, wherein an active area of each memory unit comprises thefirst source/drain region, the second source/drain region, and a channelbetween the first and second source/drain regions, and an active area isZ-shaped, comprising a main area and two extended areas, with the twoextended areas perpendicularly connecting to two ends of the main arearespectively, with the first source/drain region in one of the extendedareas and a part of the main area, and the second source/drain region inanother extended area and a part of the main area.
 27. The memory arrayas claimed in claim 19, wherein an active area of each memory unitcomprises the first source/drain region, the second source/drain region,and a channel between the first and second source/drain regions, and theactive area is T-shaped, comprising a main area and an extended area,with the end of the main area connecting to the middle of the extendedarea, and the active area is parallel to the first source/drain line orthe first bit line corresponding thereto, and the extended area isparallel to the word line corresponding thereto, with the firstsource/drain region in a part of the main area, and the secondsource/drain region in the extended area and a part of the main area.